Our continuing growth and success comes from helping our customers to maximize their return on investment. We work with the OEM's internal engineering staffs to reduce time-to-market, to lower overall UMC, and to provide products and systems that reap the benefits of Moore's Law - driving rapid and ongoing improvements in silicon device performance and cost. The project snapshots below provide a glimpse of the types of engineering efforts that have been successfully supported by the AppliedLogix team.
IP2 Project - HW Subsystem Design
Facing the Challenge:
Develop a full custom-embedded controller platform for high-performance raster image datapath in a four-color production digital press. Meet demanding requirements for RIP interaction and execution of proprietary real-time image compression and decompression functions including a parallel disk array based page store.
Unique Blend of Industry Standards and Innnovative Design:
Compact packaging: Custom Flex-ATX compatible main board with unique PCI/X planar edge connector for slot expansion. Meets full ATX form factor when main board and expander are combined.
High-performance: Freescale MPC8560 @ 833 MHz, DDR333, PCI/X-111, Gbit Ethernet. Embedded disk array (RAID-0) w/ enterprise class SATA drives.
Achieved cost targets and met aggressive schedule for product introduction.
Achieved dramatic reduction in UMC using latest silicon devices with higher levels of integration.
Increased performance and subsystem reliability with fewer components.
Met or exceeded market goals for price/performance.
This product, launched in 2006 and is still in full production today.
CCB Project—High Performance PCI/X Based Image Processing board design including Signal and Power Integity Analysis and Verification
Facing the Challenge:
Provided the OEM with board level circuit design and schematic capture, signal integrity, power integrity, and PWB design for manufacture expertise. The design was based on a high performance system FPGA suppporting (5) 2 Gbit serial transceiver links (board-to-board via 3-meter Infiniband cables) and several high clock rate synchronous memory interfaces: DDR2 @ 150 MHz, SIO RLDRAM-II @ 200 MHz, and SyncSRAMs @ 150 MHz.. Completed the detailed circuit design including the analysis and design recommendations needed to meet the FPGA PDN requirements and manage potential design margin issues due to simultaneous switching noise (SSN).
PWB Technology: 16-layer controlled impedance PWB. Deployed buried capacitance PWR // GND plane pairs and via-in-pad technology to achieve the PDN target impedance of 7 milliohms (for the FPGA core voltage rail).
Achieved 5X higher throughput at lower cost than predecessor design.
Improved system reliability with lower parts count.
Provided robust signal integrity for high-speed serial data links.
Met or exceeded challenging cost and development schedule goals.
The CCB was launched in 2007 and is still in full production.