Our client manufactures industrial instrumentation equipment that plays a key role within the semiconductor fabrication process. During their product roadmap planning, they identified an expanded set of features and functionality including the need to share data between separate pieces of equipment on the factory floor. With their internal development team stretched too thin, they turned to AppliedLogix to provide the expertise required to design and deliver the FPGA-based communications enhancements that were needed.
The solution is a production-ready VHDL-based FPGA module that allows the instrumentation to rapidly communicate and share data amongst separate pieces of equipment.
The module is backward compatible with prior versions of the product, and includes built-in-test and error detection functionality. The module also reduced software bottlenecks and improved messaging flexibility – thereby expanding the potential future product use cases.
- Increased transfer-rate supports higher-performance control algorithms
- Backward compatible with older versions of their product family
- Built-in Test (BIT) functionality
- Error detection & reporting
- Enhanced messaging flexibility
While the FPGA core was able to transfer data quickly, the software control functionality was identified as a performance bottleneck. We updated the core so that much of the message construction was automated within the FPGA. In addition, other IP cores within the FPGA could read/write data without software intervention, while software could read/write message data in parallel. We also added messaging flexibility to expand the use case possibilities for future functionality.
AppliedLogix developed a new software driver for the core (the pre-existing software driver wasn’t compatible). The driver implemented a novel, multithreaded controller to provide easy message-passing interfaces for the customer’s application-level modules.
A sophisticated, flexible testbench was developed to facilitate the module-level verification process, supporting a variable network size and a vast number of different types of errors to test. The testbench was written in VHDL, and was enveloped in an automated regression test. The end-to-end verification of the numerous message-passing and AXI-Stream interfaces was accomplished through the creative definition and deployment of a large number of Scoreboard and FIFO constructs.